High speed analog-to-digital converters (ADCs) can be used in advanced communication systems which include, for example, the 100 Gb/s and faster coherent optical transceivers and phased-array radar systems. High speed ADCs may be implemented by time-interleaving multiple (e.g., 128 or more) ADCs. For instance, by interleaving N sub-ADCs, a combined sampling rate (e.g., Fs) that is N time the sampling rate of each of the sub-ADCs may be achieved. However, impairments such as channel-to-channel gain-mismatch, offset-mismatch and non-uniform sampling-time impairments may result in degraded low spurious-free-dynamic-range (SFDR), and signal-to-noise-and-distortion-ratio (SNDR).
The channel-to-channel (e.g., between ADC channels) mismatch may include offset-mismatch, gain-mismatch, and sampling-time mismatch. The offset-mismatch, for example, can cause spurious continuous-wave (CW) unmodulated tones to appear at frequencies corresponding to multiples (e.g., 0 1 2 . . . (N−1)) of the Fs/N ratio. The gain mismatch, for instance, can result in amplitude-modulated (AM) sidebands generated from mixing of the input signal with different signal-path gains associated with each individual sub-ADC channel, whereas the sampling-time mismatch can cause frequency-dependent phase-modulation of the input signal because of different sampling-times associated with each individual sub-ADC channel. Existing solutions for mitigating these impairments are by design, at the analog circuit level. This often leads to large chip-area, high cost, high power-consumption, and undesired high design-complexity.
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